This application claims priority to Korean Application No. 2000-72940, filed Dec. 4, 2000, the disclosure of which is hereby incorporated herein by reference.
The present invention relates to methods of manufacturing integrated circuit capacitors, and more particularly, to methods of manufacturing capacitors having HSG electrodes.
As the integration of dynamic random access memory (DRAM) devices having capacitors as components of memory cells therein is increased, the area of each capacitor within each memory cell is typically decreased. Various methods of manufacturing capacitors having the same capacitance and reliability as those of the prior art or having greater capacitance and reliability than those of the prior art, yet occupying smaller lateral area, have been studied. One conventional method of increasing an effective surface area of an electrode includes forming HSG on a surface of the electrode. Particularly, as shown in FIG. 1, in a cylindrical HSG capacitor having the illustrated structure, the HSG is formed only on an internal surface of a cylindrical lower electrode 17 and an external surface of the lower electrode 17 is surrounded by an insulating layer 14 and is not used as an effective surface area of the lower electrode 17. Because the manufacturing process of the cylindrical HSG capacitor is comparatively simple, and a defect rate in its manufacture is relatively low, the cylindrical HSG capacitor is widely used. In FIG. 1, reference numeral 22 denotes a dielectric layer of a capacitor, and reference numeral 24 denotes an upper electrode of a capacitor.
The steps of manufacturing a capacitor having the above structure shown in FIG. 1 will now be described with reference to FIGS. 2 and 3. First, an interdielectric layer 10 in which devices (not shown) such as transistors are formed, is etched to form contact holes. Then, a conductive material is filled in the contact holes to form contact plugs 12. Subsequently, a mold insulating layer 14 having openings for exposing the contact plugs 12 is formed, and lower electrodes are formed in the openings. Amorphous silicon is then conformally deposited on the entire surface of the mold insulating layer 14 having the openings and the exposed contact plug 12 to form a lower electrode layer 16.
Subsequently, a planarization insulating layer 18 comprising an insulating material having generally good gap fill characteristics is formed on the lower electrode layer 16. The planarization insulating layer 18 may prevent slurry particulate or other residue of the polished lower electrode layer 16 from being attached to and contaminating concave portions of the lower electrode layer 16 when a chemical mechanical polishing (hereinafter referred to as CMP) process is subsequently performed to form the separated lower electrodes by removing/planarizing the lower electrode layer 16 down to the dotted line 20 indicated in FIG. 2.
Subsequently, the separated lower electrodes are formed by performing the CMP process on the lower electrode layer 16 down to the dotted line 20. The planarization insulating layer 18 remaining in the concave portions of the separated lower electrodes is then removed. Subsequently, HSG is formed on the surface of the concave portions of the separated and exposed lower electrodes using a conventional method, as shown in FIG. 3.
However, as shown in FIG. 3, a lower electrode 17 is slightly (to a height h) projected out of the surface of the mold insulating layer 14xe2x80x2 and is therefore not flush with the mold insulating layer 14xe2x80x2. This is because the mold insulating layer 14 is also etched to a certain degree and becomes recessed when the planarization insulating layer 18 filling the concave portions of the separated lower electrodes is removed. In general, spin-on-glass (SOG) or undoped silicate glass (USG) having good gap fill characteristics is used as the planarization insulating layer 18, and plasma enhanced tetraethylortho silicate (PE-TEOS) or phosphor silicate glass (PSG) is used as the mold insulating layer 14. In order to remove the planarization insulating layer 18, a wafer is wet etched by soaking the wafer in an etching solution including a hydrofluoric acid (HF) solution for a comparatively long time. Even though the etching selection ratio of SOG or USG with respect to PE-TEOS or PSG in the etching solution is typically very high, the etching selection ratio does not reach 100%. Thus, the mold insulating layer 14 (of FIG. 2) is typically etched back to a certain degree while the planarization insulating layer 18 is being etched.
As a result, HSG may also be formed on an upper surface and an upper portion of the lower electrode 17 (see 17xe2x80x2), and a desired capacitor as shown in FIG. 1 is not obtained. When the HSG is formed on the upper surface and the external surface of the lower electrode 17, an upper portion 17xe2x80x2 of the lower electrode 17 may become broken in a following cleaning process. In addition, HSGs, which are formed on the external upper surface of the lower electrode 17, can contact each other and this can cause adjacent electrodes to become short-circuited.
A method of forming an integrated circuit capacitor according to a first embodiment of the present invention may improve reliability by reducing the likelihood of lower electrode breakage and shorting (e.g., stringer formation) during fabrication. According to this embodiment, a method is provided that includes the steps of forming a first electrically insulating layer having an opening therein, on a semiconductor substrate. This first electrically insulating layer may extend directly on the substrate or may constitute an upper level interlayer dielectric layer. An electrically conductive electrode layer is then formed on an upper surface of the first electrically insulating layer and on a sidewall of the opening within the first electrically insulating layer. The electrically conductive electrode layer is then covered with a second electrically insulating layer. The second electrically insulating layer and the electrically conductive electrode layer are then planarized to expose the upper surface of the first electrically insulating layer and define a capacitor electrode layer on the sidewall of the opening. This capacitor electrode layer may have a U-shaped cross-section.
The capacitor electrode layer is then selectively etched-back to expose the sidewall of the opening and define a lower capacitor electrode that is recessed relative to the upper surface of the first electrically insulating layer. This selective etching step is preferably performed using the planarized second electrically insulating layer and the first electrically insulating layer as an etching mask. This step, which causes a recession of the vertical extent of the lower capacitor electrode (e.g., vertical sides of a U-shaped electrode), can be performed to improve reliability by inhibiting breakage of the ends of the lower capacitor electrode when subsequent steps are performed to etch-back layers and regions that support or surround the lower capacitor electrode. The planarized second electrically insulating layer and the upper surface of the first electrically insulating layer are then removed simultaneously to expose the lower capacitor electrode. This removal step may be performed as an etching step that selectively etches the planarized second electrically insulating layer at a faster rate than the first electrically insulating layer. Hemispherical silicon grains (HSGs) are then formed on an inner surface of the exposed lower capacitor electrode. A complete capacitor structure is then formed by forming a dielectric layer on the exposed lower capacitor electrode and then forming an upper capacitor electrode on the dielectric layer.
Methods according to another embodiment of the present invention may also include forming an interdielectric layer having a conductive plug therein, directly on a surface of a semiconductor substrate. This conductive plug may directly contact a semiconductor region within the substrate. In the event an integrated circuit capacitor is used in a dynamic random access memory (DRAM) device, the semiconductor region may constitute a source/drain region of an access transistor within a DRAM memory cell. After the conductive plug has been formed, a mold insulating layer is preferably formed on the interdielectric layer. A step is also performed to pattern the mold insulating layer to define an opening therein that exposes the conductive plug within the interdielectric layer. An electrically conductive electrode layer is then formed on an upper surface of the mold insulating layer, on a sidewall of the opening within the mold insulating layer and on the conductive plug. This electrically conductive electrode layer may be formed by conformally depositing a blanket polysilicon layer on the mold insulating layer.
The electrically conductive electrode layer is then covered with a planarization insulating layer. This planarization insulating layer also extends into the opening within the mold insulating layer. The planarization insulating layer and the electrically conductive electrode layer are then planarized to expose the upper surface of the mold insulating layer and define a capacitor electrode layer that extends on the sidewall of the opening and on the conductive plug. To reduce the likelihood of breakage of the capacitor electrode layer, the capacitor electrode layer is then selectively etched back to expose the sidewall of the opening and define a lower capacitor electrode that is recessed relative to the upper surface of the mold insulating layer. The planarization insulating layer is then removed along with a portion of an upper surface of the mold insulating layer. This removal step exposes an inner surface of the lower capacitor electrode. This removal step may comprise etching the planarization insulating layer at a first rate while simultaneously etching the upper surface of the mold insulating layer at a second rate slower than the first rate. Hemispherical silicon grains (HSGs) are then formed on the inner surface of the lower capacitor electrode. The mold insulating layer may be etched again to expose an outer surface of the lower capacitor electrode. A dielectric layer and upper capacitor electrode layer are then formed on the lower capacitor electrode.